Free Open-Source FPGA-Simulators
| Simulator name | License | Author/company | Supported languages | Description |
|---|---|---|---|---|
| GPL Cver | GPL | Pragmatic C Software | V1995, minimal V2001 | This is a GPL open-source simulator. It is a pure simulator. This simulator is not fully IEEE 1364-2001 compliant. It does not support generate and constant functions. |
| Icarus Verilog | GPL2+ | Stephen Williams | V1995, V2001, V2005, limited SV2005/SV2009 | Also known as iverilog. Good support for Verilog 2005, including generate statements and constant functions. |
| LIFTING | A. Bosio, G. Di Natale (LIRMM) | V1995 | LIFTING (LIRMM Fault Simulator) is an open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. | |
| OSS CVC | Perl style artistic license | Tachyon Design Automation | V2001, V2005 | CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode. Source code is available under a Perl style artistic license. |
| TkGate | GPL2+ | Jeffery P. Hansen | V1995 | Event driven digital circuit editor and simulator with tcl/tk GUI based on Verilog. Includes Verilog simulator Verga. |
| Verilator | GPL3 | Veripool | Synthesizable V1995, V2001, V2005, SV2005, SV2009, SV2012, SV2017 | This is a very high speed open-source simulator that compiles synthesizable Verilog to multithreaded C++/SystemC. |
| Verilog Behavioral Simulator (VBS) | GPL | Lay H. Tho and Jimen Ching | V1995 | Supports functions, tasks and module instantiation. Still lacks a lot of features, but this release has enough for a VLSI student to use and learn Verilog. Supports only behavioral constructs of Verilog and minimal simulation constructs such as 'initial' statements. |
| VeriWell | GPL2 | Elliot Mednick | V1995 | This simulator used to be commercial, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364-1995. |
| ISOTEL Mixed Signal & Domain | GPL | ngspice and Yosys communities, and Isotel | V2005 | Open-source mixed signal ngspice simulator in combination with verilog synthesis software called Yosys and Isotel extension for embedded C/C++ (or other) co-simulation. |
| Simulator name | License | Author/company | Supported languages | Description |
|---|---|---|---|---|
| GHDL | GPL2+ | Tristan Gingold | VHDL-1987, VHDL-1993, VHDL-2002, partial VHDL-2008 | GHDL is a complete VHDL simulator, using the GCC technology. |
| Icarus Verilog | GPL2+ | Maciej Sumiński Stephen Williams | It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions. | VHDL preprocessor added that converts VHDL to Verilog |
| NVC | GPL3 | Nick Gasson | VHDL-1993 | NVC is a GPLv3 VHDL compiler and simulator aiming for IEEE 1076-2002 compliance. See these blog posts for background information. NVC has been successfully used to simulate several real-world designs. |
| YoSys | GPL3 | UnKnown | Verilog-2005 design | Yosys is a framework for Verilog RTL synthesis. |
| KEY | |
| Tag | Description |
|---|---|
| V1995 | IEEE 1364-1995 Verilog |
| V2001 | IEEE 1364-2001 Verilog |
| V2005 | IEEE 1364-2005 Verilog |
| SV2005 | IEEE 1800-2005 SystemVerilog |
| SV2009 | IEEE 1800-2009 SystemVerilog |
| SV2012 | IEEE 1800-2012 SystemVerilog |
| SV2017 | IEEE 1800-2017 SystemVerilog |
| VHDL-1987 | IEEE 1076-1987 VHDL |
| VHDL-1993 | IEEE 1076-1993 VHDL |
| VHDL-2002 | IEEE 1076-2002 VHDL |
| VHDL-2008 | IEEE 1076-2008 VHDL |
See also
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