PWD:ISE-Source-File-Types
Xilinx Source-File-Types ISE
Source File Types
Source File Types
To use and manage source files in Project Navigator,
you must add the source files to the project. You can either create
new source files in Project Navigator and automatically add them to the
project, or you can add existing source files to the project. Following
is a list of the supported source types. Some source types may not be available, depending on your design properties
(top-level module type, target device, and synthesis tool).
Note For a list of all the file types generated by
the ISE® software, see the "Xilinx® Development System Files"
appendix in the Command Line Tools User Guide.
File Type
|
Extension
|
Icon
|
Description
|
New Source
Wizard Behavior/Tool Launched
|
|---|---|---|---|---|
Block RAM Memory Map (BMM
File)
|
.bmm
|  |
Used in PowerPC® and MicroBlaze™ processor
designs to describe the organization of Block RAM memory.
Note Only one BMM Module is allowed per project.
|
Opens the file in the text
editor you specify in the Editors page of
the Preferences dialog box. The CPU executable code is automatically
inserted in the configuration file during design implementation.
|
ChipScope Definition and
Connection (CDC File)
|
.cdc
|  |
Contains generic information
about the trigger and data ports of the ChipScope™ core.
|
Adds the file to the
project. Double-click the CDC file in the Hierarchy pane of the Design panel to
run the implementation process and launch the ChipScope Pro Core Inserter.
For details, see the ChipScope Pro Tool
Debugging Overview.
Note The ChipScope Pro tool must be installed for this source type to be available.
|
Electronic Data Interchange
Format (EDIF)
|
.edn, .edf, .edif, .sedif
|  |
Specifies the design netlist
in an industry standard file format.
|
N/A
Must be generated
by a third-party design entry tool and added to the project.
Note You can only add an EDIF file as a top-level module,
not as a lower-level module. If you are using hierarchical EDIF files,
lower-level EDIF files are automatically processed during the implementation
process.
|
ELF
|
.elf
|  |
Contains an executable
CPU code image.
Note Only one ELF file is allowed
per project.
|
N/A
Must be generated
by the Data2MEM command line tool and added to the project.
|
Embedded Processor
|
.xmp
|  |
Embedded microprocessor
project file created with Xilinx Platform Studio.
|
Launches the Xilinx Platform Studio in
which you can define the embedded processor system portion of your
design. For details, see the Embedded Development Kit Documentation.
|
Implementation Constraints
File
also known as User Constraints File (UCF)
|
.ucf
|  |
Contains user-specified
logical constraints.
|
Adds the file to the
project. Double-click the UCF file in the Hierarchy pane of the Design panel, or
double-click a Constraints Entry process in the Processes pane to
open the file.
You can assign multiple UCFs to the top-level
module. For details, see Constraints Entry Methods.
|
IP (Architecture Wizard)
|
.xaw
|  |
Contains predefined logic
functions that configure architecture features or modules.
|
Launches one of the Xilinx Architecture Wizards
in which you can define your IP. For details, see Working with Architecture Wizard IP.
|
IP (CORE Generator)
|
.xco
|  |
Contains predefined logic
functions.
|
Launches one of the Xilinx IP
core customization tools in which you can define your IP. For details,
see Working with CORE Generator™ IP.
|
Memory Definition (MEM File)
|
.mem
|  |
Used to define the contents
of memory (RAMB4 and RAMB16).
Note Only one MEM file
is allowed per project.
|
Opens the file in the text
editor you specify in the Editors page of
the Preferences dialog box. The CPU executable code is automatically
inserted in the configuration file during design implementation.
|
Schematic
|
.sch
|  |
Contains a schematic design.
|
Opens the schematic file
in the Project Navigator Workspace. For details, see the Schematic Overview.
|
System Generator module
|
.sgp
|  |
Contains Digital Signal Processing (DSP) system
module created with System Generator for DSP.
|
N/A
Must be added
to the project.
|
Targeted device, package,
and speed grade
|
N/A
|  |
Shows the targeted device,
package, and speed grade.
|
N/A
|
Undefined
|
N/A
|  |
Contains an instantiated
module that has not been added to the ISE project but is referenced
by a source file in the ISE project.
|
N/A
|
User Document
|
Multiple file types
|  |
Contains user information
that is not implemented with the project, for example, supporting
documentation.
|
N/A
Must be added
to the project.
|
Verilog Module
|
.v
|  |
Contains Verilog design
code.
|
Opens the file in the text
editor you specify in the Editors page of
the Preferences dialog box.
|
Verilog Test Fixture
|
.v
|  |
Defines the stimulus to
the ports of an HDL file.
|
Prompts you to associate
the file with a Verilog source module and then opens a skeleton test
bench file in the text editor you specify in the Editors page of
the Preferences dialog box.
|
VHDL Library
|
N/A
|  |
Contains a collection of
VHDL packages.
|
Adds a new directory to
the vhdl library directory in the Libraries panel.
|
VHDL Module
|
.vhd
|  |
Contains VHDL design code.
|
Opens the file in the text
editor you specify in the Editors page of
the Preferences dialog box.
|
VHDL Package
|
.vhd
|  |
Contains definitions, macros,
sub-routines, supplemental types, subtypes, constants, functions,
and other files.
|
Opens the file in the text
editor you specify in the Editors page of
the Preferences dialog box.
|
VHDL Test Bench
|
.vhd
|  |
Defines the stimulus to
the ports of an HDL file.
|
Prompts you to associate
the file with a VHDL source and then opens a skeleton test bench file
in the text editor you specify in the Editors page of
the Preferences dialog box.
|
© Copyright 1995–2009, Xilinx®
Inc. All rights reserved.
